1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a lower plate for a capacitor.
2. Background of the Related Art
A memory cell of a DRAM (dynamic random access memory) includes two main parts, a field effect transistor and a capacitor. In reducing the size of the capacitor to increase the degree of integration of a memory device, the capacitance is reduced, which results in the following problems.
First, a soft error can occur. Soft error occurs when the DRAM discriminates information of xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 by the amount of electric charge accumulated in the capacitor. This occurs when pairs of electron-micropyle are additionally generated by alpha particles which affect the amount of electric charge in the capacitor causing the disturbance of information stored in the memory device, which is called as a soft error.
Second, the operating speed of the DRAM is reduced. In the DRAM, a refresh operation for periodically charging the electric charge accumulated in the capacitor of each cell is required. As the capacitance becomes smaller, the refresh time between each periodic charge becomes shorter. Since other operations are stopped during the refresh operation, the operating speed of a semiconductor device is reduced due to the decrease in refresh time.
Thus, a number of methods for fabricating a capacitor having a sufficient capacitance with a reduced area in a semiconductor substrate occupied by the capacitor have been developed. These methods can be divided into the study of the structure of the capacitor and the study of the materials of the capacitor.
With respect to the structure of the capacitor, the main areas of development are the decreasing of the thickness of a dielectric film, the increasing in the effective surface area of a lower plate of the capacitor, and the like. With respect to the materials of the capacitor, the main area of development is the search for an alternative dielectric film capable of replacing a conventional silicon oxide film.
However, the decreasing of the thickness of the dielectric film has its limitations due to leakage current characteristics, and it is difficult to replace the silicon oxide film with another material because the conventional process would have to be changed. Hence, studies are under way for the purpose of maintaining the capacitance of a capacitor by increasing the effective surface area of a lower plate of a capacitor plate.
The conventional method for fabricating a capacitor will now be described with reference to the accompanying drawings. Overall, the capacitor is fabricated by solidifying the lower plate of the capacitor into a cup shape, wherein the surface area of the lower plate is maximized by forming HSG (hemispherical silicon grain) on the surface of the lower plate.
First, as illustrated in FIG. 1a, a plurality of respective devices 101 are formed on the top surface of a semiconductor device 100, and then a planarization layer 102 made of insulating material is formed on a top surface of the respective devices 101. Next, a contact hole is formed on the planarization layer 102, and is filled with conductive material, thereby forming a contact plug 103 so that the plug is electrically connected to the semiconductor device. Then, a nitride film 104 is formed on the planarization layer 102 and a top surface of the contact plug 103. Then, a silicon oxide film 105 is deposited by a plasma chemical vapor deposition on a top surface of the nitride film 104.
As illustrated in FIG. 1b, the nitride film 104 and the silicon oxide film 105 are partially etched to thus form an opening 110 at the nitride film 104 and the silicon oxide film 105, so that the top surface of the contact plug 103 is completely exposed.
Next, as illustrated in FIG. 1c, an amorphous silicon layer 111 is deposited on the front surface of the structure of FIG. 1b by chemical vapor deposition.
Next, as illustrated in FIG. 1d, an SOG (spin on glass) film 112 is formed on the top surface of the amorphous silicon layer 111 and in the opening 110, then an etchback process is performed to thus let the SOG film 112 remain only in the opening 110.
Next, as illustrated in FIG. 1e, a chemical mechanical polishing process is performed such that the amorphous silicon layer 111 on the top surface of the silicon oxide film 105 is removed.
Next, as illustrated in FIG. 1f, the silicon oxide film 105 and the SOG film 112 are removed by wet etching using an oxide film etching solution, thereby leaving only an amorphous silicon pattern 111 of a cup shape. A hemispherical silicon grain (HSG) layer 113 is formed on the top surface of the silicon pattern 111, thus completing the formation of the lower plate of the capacitor.
However, the above-described conventional method for fabricating a capacitor has the following problems.
First, HSG is formed on the silicon oxide film which causes neighboring lower plates of a capacitor to be electrically short-circuited by the HSGs formed on the oxide film. Second, a bridge phenomenon occurs when the HSGs on side walls of the lower plate stick to each other.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Accordingly, it is an object of the present invention to provide a method for fabricating a lower plate of a capacitor having a high reliability and capable of increasing the capacitance by preventing a bridge between lower plates of the capacitor.
To achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device according to the present invention which includes forming a planarization layer on a semiconductor substrate, forming a contact hole on the planarization layer, forming a conductive plug to be electrically connected to the semiconductor substrate in the contact hole, forming a first nitride film on the planarization layer and the top surface of the conductive plug, forming a first oxide film on the top surface of the first nitride film, forming a trench around the conductive plug by partially etching the first oxide film, forming a second nitride film in the trench, etching and removing the first oxide film, forming a second oxide film on the top surface of the second nitride film and the first nitride film, exposing the top surface of the conductive plug by etching the second nitride film and the first nitride film, forming an amorphous silicon layer pattern on the top surface of the conductive plug and the side walls of the second oxide film, selectively etching and removing the second oxide film, forming silicon grains on the surface of the amorphous silicon layer to thus increase the surface area of the lower plate of the capacitor, and etching and removing the second nitride film.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein forming a second nitride film in the trench includes forming the second nitride film in the trench and on the top surface of the first oxide film, and removing the second nitride film on the top surface of the first oxide film.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein removing the second nitride film is an etchback process or chemical mechanical polishing process.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein the first oxide film is a silicon oxide film formed by the chemical vapor deposition method using TEOS.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein the second oxide film is a silicon oxide film deposited by a high temperature, low pressure chemical vapor deposition method.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein exposing the conductive plug is a process of sequentially anisotropic etching the second oxide film and the first nitride film without using a mask.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein forming an amorphous silicon layer pattern includes depositing the amorphous silicon layer on the top surface of the conductive plug, top surface and side walls of the second oxide film, and top surface of the second nitride film, thickly forming a photoresist layer on the amorphous silicon layer so that the top surface of the amorphous silicon layer is not exposed, etching back the photoresist layer so that the top surface of the amorphous silicon layer is exposed, and removing the amorphous silicon layer on the top surface of the second nitride film.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein the step of removing the amorphous silicon layer on the top surface of the second nitride film is an etchback process.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein the step of removing the amorphous silicon layer on the top surface of the second nitride film is a chemical mechanical polishing process.
In addition, to achieve the above object, there is provided a method for fabricating a lower plate of a capacitor of a semiconductor device, wherein the removing of the second nitride film is done with a wet etching method using a phosphatic (H3PO4) solution.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.